Conventional double data rate fourth generation (DDR4) interfaces are specified to operate at a data rate up to 3.2 gigabits/second. At such high data rates, signal integrity becomes an issue. A continuous-time linear equalizer (CTLE) circuit is widely used to compensate for channel insertion loss and return loss. A slicer circuit differentiates the compensated signal. Under various power supply conditions, a CTLE output common mode voltage can become too high for the slicer circuit to properly differentiate. Tests show receiver malfunctions at high power supply voltages. Under large input voltage swing conditions, receiver setup times result in poor timing margins and poor data eye-diagram symmetry.
It would be desirable to implement high signal voltage tolerance in a single-ended memory interface.